1. Field of Invention
The present invention relates to memory ICs having bit lines to record and reproduce data in memory cells, such as ROMs, RAMs and the like.
2. Description of Related Art
FIGS. 4(a) and 4(b) show a related art memory IC. FIG. 4(a) shows a circuit diagram of a memory cell 40 that is a main part of the memory IC, and FIG. 4(b) shows a timing chart of operations of the memory cell 40. In FIG. 4(a), an N-type MOS transistor (hereafter “N-Tr”) 4 has a drain D connected to a bit line BL, a gate G to a word line WL, and a source S to an electrode on one side of a capacitor C4.
The other electrode of the capacitor C4 is connected to a plate electrode P. A potential difference is present between the plate electrode P and the bit line BL, and the drain D and source S of the N-Tr4 and the capacitor C4 are serially interposed between the two. By a control signal on the word line WL, the N-Tr 4 functions as a timing switch, and a charge representing Hi-Low data (hereafter “Data”) present on the bit line BL is charged or discharged to thereby compose the memory cell 40 that reads and writes data.
The memory cell 40 writes or reads Data4 indicated in FIG. 4(b) at timings in which the transistor therein shifts from OFF state to ON state. The N-Tr4 has its gate G connected to the word line WL, so that by switching the potential on the word line WL between Hi and Low, the N-Tr4 can be ON-OFF controlled at appropriate timings.
Referring to FIGS. 4(a) and (b), when a word signal that is formed with a pulse waveform rises from Low to Hi, the N-Tr4 turns ON as its gate G is set to Hi, and an electric charge is charged in the capacitor C4, such that Data4 is recorded in the memory cell 40. When the word signal falls from Hi to Low, no information processing takes place. Then, when the word signal that has once fell to Low rises again to Hi, the N-Tr4 turns ON, such that Data4 is outputted as a bit (out) signal to the word line WL.
Data4 may be written or read while intermittingly giving ON times at substantial intervals to the N-type transistor N-Tr4 indicated here as an example. In this manner, information is processed at timings when each one of pulses of the word signal rises from Low to Hi. In this case, a half of the operation contains information blank time, compared to a case in which information is continuously processed at both timings when each of the pulses of the word signal rises from Low to Hi and falls from Hi to Low, and therefore the operation is not continuous and instead is rather intermittent.
The speed of writing Data4 in the memory cell 40 is determined by a cycle time Tc. The cycle time means a shortest time starting from a moment when an address is given to a memory to read or write until a moment when an address for the next reading or writing can be given. Therefore, the higher the operation frequency of the memory IC and the shorter the cycle time Tc, the more precisely and the greater amount information can be processed to read and write.